module compare (
  input signed [7:0] iA,
  input signed [7:0] iB,
  output oEQ,       // 等于
  output oNEQ,      // 不等于
  output oGT,       // 大于
  output oGT_EQ,    // 大于等于
  output oLT,       // 小于
  output oLT_EQ     // 小于等于
);
 
assign oEQ    = (iA == iB),
       oNEQ   = (iA != iB),
       oGT    = (iA >  iB),
       oGT_EQ = (iA >= iB),
       oLT    = (iA <  iB),
       oLT_EQ = (iA <= iB);
 
endmodule